1. Field of the Invention
The present invention relates to discrete-time electronic circuits, and more particularly, to a low power discrete-time electronic circuit with a variable power supply.
2. Description of the Prior Art
Electronic circuits are key components in a plethora of consumer, industrial, and military devices and systems. With each generation of circuit technology, electronic circuits generally shrink in size, gain speed, and consume less power. For mobile devices, low power consumption is a key requirement.
Mixed signal circuits, such as analog to digital converters (ADCs), digital to analog converters (DACs), are used in a wide range of products. Many architectures are available with their respective trade-offs. One such architecture is a discrete-time architecture, which is popular for its high integrability and precision. FIG. 1 is a diagram illustrating two stages 110, 120 of a pipeline ADC 10. Sub-ADCs 111, 121 receive input signals, and output a digital bit based on level of the input signal received, e.g. 1 or 0, or −1, 0, or +1. The digital bits are combined by digital combiner circuits 130 to output a digital sequence representing magnitude of the analog input signal. Each stage 110, 120 also includes a multiplying DAC (MDAC) 112, 122 that outputs an analog signal having a level corresponding to the digital bit outputted by the respective sub-ADC 111, 121. Adders 113, 123 combine the original input signal with the analog signal from the MDAC 112, 122, and the combined signal is amplified by a gain stage 114, 124 for output to the next stage. In practice, the MDAC 112, 122 may be responsible for the functions of the adder 113, 123 and the gain stage 114, 124. Also, each pair of stages 110, 120 may share one MDAC. Thus, the MDACs 112, 122 may be a single, shared MDAC.
FIG. 2 illustrates operation of the first-stage sub-ADC 111 in a first phase Φ1 and a second phase Φ2, and operation of a second-stage sub-ADC 121 in the first phase Φ1 and the second phase Φ2. For the first-stage sub-ADC 111, in the first phase Φ1, differential input capacitors C1, C2 are charged by differential input signals INP, INN, and output of an amplifier 1111 is latched by a latch 1112 at transition from phase Φ1 to phase Φ2. In the second phase Φ2, the differential input capacitors C1, C2 are electrically connected to offset voltages (Vref−Vcm), (Vrefb−Vcm) respectively. For the second-stage sub-ADC 121, in the first phase Φ1, differential input capacitors C3, C4 are electrically connected to offset voltages (Vref−Vcm), (Vrefb−Vcm) respectively. In the second phase Φ2, the differential input capacitors C3, C4 are charged by differential input signals INP, INN, and output of an amplifier 1211 is latched by a latch 1212 at transition from phase Φ2 to phase Φ1.
FIG. 3 illustrates operation of the MDACs 112, 122 of FIG. 1, where the MDACs 112, 122 are a single, shared MDAC. In the first phase Φ1, capacitors C5, C6 are charged by input signals INP, INN, and capacitors C7, C10 are charged by reference signals −VREF, +VREF, respectively. In the second phase Φ2, the capacitors C5, C6 are switched at their outputs to electrically connect to an amplifier 150 for amplification, and are switched at their inputs to reference signals +VREF, Vcm, or −VREF based on outputs of the sub-ADCs 111, 121. Output terminals of the capacitors C7, C10 are switched to outputs of the amplifier 150, and input terminals of the capacitors C7, C10 are switched to Vcm. Thus, the MDACs 112, 122 share the amplifier 150 to perform digital to analog conversion, addition/subtraction, and amplification.
Please refer to FIG. 4, which is a diagram illustrating operating current of the amplifiers 1111, 1211, 150 throughout the various phases Φ1, Φ2 described above. As shown in FIG. 4, fixed high current is supplied in each operating phase of the pipeline ADC 10, such that the pipeline ADC 10 does not provide significant power savings to the user.